fromgof/TridentVision
Implement yolov26m using a complete FPGA, without any C language code. Requires 160K LUTs and 386 DSP cores (based on Xilinx XC7K325T).
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README & documentation
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在成本敏感的 Xilinx Kintex-7 FPGA 上运行的端到端 YOLOv26m 目标检测系统:GigE 工业相机进,HDMI 实时画框出,全程无 PC 参与。 End-to-end YOLOv26m object detection on a cost-sensitive Xilinx Kintex-7 FPGA: GigE industrial camera in, HDMI bounding boxes out — no PC involved. English README 见文末 / English version at the bottom TridentVision 把 YOLOv26m 检测网络完整部署到一块 Kintex-7 K325T 自定义板上: 时序:rrC 基线 WNS +0.088 / WHS +0.051 / 0 失败端点(impl 实测,见 docs/reports/hdmitimingimpl.rpt)。 环境:Vivado 2024.1(含 Vitis/xsct)、Python 3(训练需 CUDA + PyTorch + ultralytics,见 training/README.md)、Icarus Verilog(仿真,可选)。 详见 docs/trainingexportguide.md。 上电后读 FP0/FP1/FP2 得 96bit 指纹 → ipcore/deliverable/vendor/keygen/keygen.bat → 写 KEY0/KEY1/KEY2。详版见 §9 与 ipcore/deliverable/customer/doc/TridentVisionIP核客户集成指南.md。 KC705 构建路径(D5 说明):ipcore/deliverable/customer/examplekc705/ 的构建脚本以 DCP 例化 IP 核。本仓库不带 dcp——两条路:① 从 Release 页下载 tv3ipcore.dcp;② 用 ipcore/rtl/ 源码在 Vivado 中自行 packageip 生成。 本仓库全量公开一套芯片 DNA 绑定 license 体系,作为 FPGA IP 保护的教学样本: 相机半锁死案(docs/gigedebugsummary.md 第十九章):消费端消失 → 相机流引擎楔死为 1.3fps 涓流(PC 直连 98fps 满血,排除相机硬件)。固件侧落地 GUARD 病态防护:停驻率 EMA(>2048 进入 / <1024 解除回差)→ 病态期冻结画框(SCRATCH[32/35/36] 可观测),实测病态期 shown=0、输入框消退、识别维持 10.2fps 不雪崩。完整案例索引见 docs/troubleshootingindex.md。 详版:docs/optimizationroadmap.md。 本项目整体以 AGPL-3.0 发布(见 LICENSE),包括全部自研 RTL、固件、C 模型与训练脚本。 Release 附件(不入 git 树):yolo26m.pt(44MB)、tv3ipcore.dcp(14MB,KC705 集成用)。 见…
Read the full README ↗ · Preview checked 2026-10-30T12:49:25.812Z
Inside the original README — Document outline
- TridentVision
- 1. 项目简介
- 演示效果
- 2. 特性
- 3. 实测性能(全部为板上实测值,出处逐图标注)
- 产线帧率演进
- REARCH 引擎提速六杠杆(验证线 0.831 → 12.897 fps,15.5×)
- 显示税归因与逐项收益(0 收益项如实保留)
- 帧耗时分解(优化前后)
- K325T 资源占用(数据源:docs/reports/hdmiutilizationimpl.rpt)
- 验证与回归套件
- QAT 训练收敛
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Links from the README
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- English README 见文末 / English version at the bottom
- docs/trainingexportguide.md
- docs/deployguide.md
- docs/debugguide.md
- docs/optimizationroadmap.md
- docs/troubleshootingindex.md
- ipcore/deliverable/customer/doc/TridentVisionIP核客户集成指南.md
- docs/gigedebugsummary.md
- docs/REARCHV1OPTIMIZATIONSUMMARY.md
- docs/REARCHFPSDISSECTION.md
- docs/YoloV26MFPGAV1.0总结.md
- LICENSE
Documentation belongs to its respective authors. Reported project/model license: AGPL-3.0. A listing is not a grant of reuse or training rights. Confirm the document’s own terms at the source.
What this repository does
Implement yolov26m using a complete FPGA, without any C language code. Requires 160K LUTs and 386 DSP cores (based on Xilinx XC7K325T).
Repository facts
- Owner
- fromgof
- Primary language
- Verilog
- Stars
- 147
- Forks
- 41
- Open issues + pull requests
- 0
- License
- AGPL-3.0
- Archived
- No
- Default branch
- main
- Created
- 2026-09-09T12:53:47.000Z
- Last push
- 2026-09-09T13:07:47.000Z
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